1. Field of the Invention
This invention relates generally to semiconductor devices, and, more particularly, to a physical arrangement of a cache memory system.
2. Description of the Related Art
In modern computer systems, a significant factor in determining the overall performance of the computer system is the speed with which it accesses memory. Generally, faster memory accesses result in higher performance. Unfortunately, however, high-speed memory is expensive. Thus, it is generally economically unfeasible to construct a computer system that uses high-speed memory components as its main memory.
To provide a computer system with enhanced speed that is still economical to produce, many modern computer systems employ a memory system that consists of a hierarchy of several different levels. That is, the computer system has a relatively large and inexpensive main memory, which may be comprised of a relatively slow dynamic RAM, or the like, and at least one relatively small high-speed cache. The computer system attempts to maximize its speed of operation by utilizing the high-speed cache as much as possible, as opposed to the slow main memory. In fact, many computer systems have prefetch and cache management instructions that are highly successful when used with software that can predict the portions of main memory that are likely to be needed. The prefetches and cache management instructions can optimize moving data between the main memory and the caches. Thus, as long as the predictions are accurate, each request for memory should result in a hit in the cache, and faster overall operation.
Faster operaton of the cache may be achieved by locating the cache on the same die as the microprocessor. Such an arrangment minimizes the length of the electrical interconnections/lines extending between the cache and the microprocessor. Shorter line lengths translate into faster operation because signals take less time to travel therebetween.
There are, however, drawbacks to locating the cache on the same die as the microprocessor. For example, locating the cache on the die will substantially increase the number of transistors on the die. As the number of transistors increases, so does the error rate. That is, locating the cache on the die will increase the likelihood that the overall device will not operate properly, requiring the relatively expensive microprocessor to be scrapped along with the relatively inexpensive cache. Further, if the cache is located on the die, it is problematic to have different size caches on different microprocessor products. That is, it may be desirable to have several products that use the same microprocessor core with a different size or number of caches. Each of these products may have to undergo an expensive redesign and verification process before being released for production.
Locating the cache external to the microprocessor die has the advantage of flexibility in manufacturing. That is, the same microprocessor may be packaged with a variety of sizes and numbers of external caches without the need for separate designs. Moreover, a defect in the relatively inexpensive cache does not affect the usability of the expensive microprocessor die. As discussed above, however, the external cache ordinarily operates at a slower speed than a similar internal cache. Further, an external cache is ordinarily permanently soldered to a printed circuit board, such as a mother or daughter board. Thus, the external microprocessor takes up valuable printed circuit board real estate, and is difficult to update. That is, because the cache is soldered in place it cannot be easily upgraded by the end user when larger, faster, or less expensive caches become available.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a semiconductor module is provided. The semiconductor module is comprised of a die, a casing and a plurality of electrical connections. The casing extends about the die and defines a plurality of openings extending therethrough. The openings are arranged in a first preselected pattern to receive pins of a semiconductor device therein. A plurality of electrical connections are disposed in at least a portion of the plurality of openings and are adapted to electrically communicate with the pins of the semiconductor device inserted therein and the die.
In another aspect of the present invention, a semiconductor stack is provided. The semiconductor stack is comprised of a first semiconductor device, a second semiconductor device, and a socket. The first semiconductor device has a plurality of pins extending therefrom and arranged in a first preselected pattern. The socket is adapted to receive the plurality of pins. The second semiconductor device is disposed between the socket and the first semiconductor device and includes a die, a casing, and a plurality of electrical connections. The casing extends about the die and defines a plurality of openings extending therethrough. The openings are arranged in a first preselected pattern to receive the pins of the first semiconductor device. The plurality of electrical connections are disposed in at least a portion of the plurality of openings. The electrical connections are adapted to electrically communicate with the pins of the first semiconductor device inserted therein and the die.